This essay Sharfaraz Hassan CSC 33200 has a total of 528 words and 3 pages.
Sharfaraz Hassan CSC 33200
Suppose we make the following change. We add two new registers in the CPU: IPC and IPSW. When interrupt occurs, the old PC is push onto IPC and the old PSW is pushing onto IPSW (so we don't push PC, PSW onto the stack) Similarly, when the RTI is executed , PC and PSW get values from IPC and IPSW respectively (not from the stack) There are no other changes. Explain what problem will arise due to this change? (50 words or less)
1) The value side of the registers may get overridden if multiple interrupts are occurring at the same time. Since each register can only hold one value, unlike a stack tha t can hold multiple values, the overridden values of PC and PSW will be irretrievable , which may result to data loss.
2. Assume the following:
(a) The interrupt vector is properly loaded
(b) Somehow, all the service routines have been wiped out -- they have all become zeroes
(c) The leftmost bit of the OP code of any valid instruction is now 1
Now suppose a user executes a system call, what will happen? (50 words or less)
2) Since the service routines have all become 0 , the system call that the user requested will not be performed since no valid system calls exist, as a result.
3. The mode bit is not longer part of the PSW register, but is a separate bit. Whenever an interrupt occurs, the hardware automatically changes the mode bit to 'supervisor'. Whenever the RTI instruction is executed in supervisor mode the hardware changes the mode bit to 'user'. ( the hardware takes these actions in addition to the usual action that it takes in the interrupt mechanism discussed in class). Will this mechanism work? (50 words or less)
3) This mechanism will work. Since the mode bit is being changed at t he right time s - directly after an interrupt occurs is the first time it changes and then during RTI execution is the second time it changes. Therefore, t his me chanism will work the same way as if it was part of the PSW register.
4. Consider a system with two CPUs. Suppose they share a single control stack - the stack where old PC, PSW values are stored when an interrupt occurs. When the RTI is executed, the stack is popped (such that the 2 topmost entries are removed) to reload the PC, PSW values. What can go wrong with this scheme? (50 words or less)
4) Since two CPUs share one control stack , both of the CPUs can push their PC and PSW values into the control stack if both of them . This can cause a problem because the first CPU might pop the old values of PC and PSW and incorrectly assign them to its PC and PSW registers that were pushed onto the stack by the second CPU, or vice versa. Therefore, the first CPU's registers may have the old value s of the second CPU's registers. Therefore, this can result in data loss.